1. Field
Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a semiconductor device having buried bit lines and a method for fabricating the same.
2. Description of the Related Art
Most semiconductor devices include transistors. For example, in a memory device, such as a DRAM, a memory cell includes a MOSFET. In general, since source/drain regions of a MOSFET are formed in a surface of a semiconductor substrate and a planar channel is formed between the source region and the drain region. Such a general MOSFET is referred to as a planar channel transistor.
As demands for improvements in the degree of integration and performance of a memory device increase, a technology for fabricating a MOSFET is faced with physical limitations. For example, as the size of a memory cell shrinks, the size of a MOSFET shrinks. As a result, the channel length of the MOSFET is shortened. When the channel length of a MOSFET is shortened, the properties of maintaining data are likely to deteriorate, and the characteristics of the memory device may be degraded.
In consideration of these problems, a vertical channel transistor (VCT) has been suggested in the art. In the vertical channel transistor, junction regions are formed at respective ends of a pillar, and any one junction region is connected with a bit line. The bit line is formed by being buried in a trench defined between pillars, and accordingly, is referred to as a buried bit line (BBL).
Two memory cells, each including a VCT and a BBL, are adjacent to one BBL. Therefore, the one BBL is formed in a space (trench) between memory cells, and an OSC (one-side-contact) process is performed to connect one memory cell with one BBL. The OSC process allows each BBL to be brought into contact with any one of two adjacent memory cells. Thus, the OSC process is also referred to as a single-side-contact (SSC) process. Generally, in a memory device that uses a planar channel transistor, in order to connect the planar channel transistor with a bit line, a contact plug process with a high aspect ratio is required. Conversely, in the case of using a vertical channel transistor and a buried bit line, since the vertical channel transistor and the buried bit line may be brought into direct contact with each other, a contact plug process is not required. Hence, the parasitic capacitance of the bit line may be reduced.
FIG. 1 is a cross-sectional view illustrating buried bit lines according to the conventional art.
Referring to FIG. 1, a plurality of bodies 14, which are separated by trenches 13, are formed in a substrate 11. The bodies 14 are formed through an etching process for the substrate 11, using a hard mask layer 12. A protective layer 15 is formed on the side walls of the bodies 14 and on the surfaces of the substrate 11 that define trenches 13. Open parts 17 are defined in the protective layer 15 through an OSC process. Each open part 17 exposes a sidewall of each body 14. Buried bit lines 16 are formed in the trenches 13. The buried bit lines 16 are connected with the bodies 14 through the open parts 17. Each buried bit line 16 is connected with one of two adjacent bodies 14. While not shown in the drawing, the upper portion of each body 14 includes a pillar in which source/drain regions and a channel of a vertical channel transistor are formed.
As can be seen from FIG. 1, in order to connect each buried bit line 16 to the sidewall of one of the adjacent bodies 14, an OSC process is used. In order to implement the OSC process, various methods such as a liner layer and a tilt ion implantation process, an OSC mask process, and the like have been proposed.
However, these methods fail to form a uniform and reproducible OSC structure due to difficulties in processing. Also, as the level of integration increases, a problem occurs in that the distance between adjacent buried bit lines 16 becomes narrow and parasitic capacitance CB between adjacent buried bit lines 16 increases. Since the buried bit lines 16 are brought into contact with the bodies 14, the parasitic capacitance CB between buried bit lines 16 acts as a capacitance between the body 14 and the buried bit line 16. Accordingly, because the distance between adjacently buried bit lines 16 becomes narrow, the parasitic capacitance CB increases markedly.
If the parasitic capacitance CB between buried bit lines increases in this way, the operation of a device may become impossible.